1. Field of the Invention
The present invention relates to integrated circuits and, in particular, to systems and methods for generating adjustable delay.
2. Discussion of Related Art
Improvement of both design techniques and process technology have yielded considerable increase in the speed of integrated circuit (IC) devices. Many IC devices operating at high clock rates have precise timing requirements. For example, new generations of memory chips communicate with other chips in a system at increasingly faster speeds. Thus, the time between applying a read signal in one clock domain, sampling in another clock domain, and generating an output signal in response to the read signal in the system is precisely controlled.
Generally, it is desirable to implement a delay chain circuit that generates linear and monotonic delay steps because circuits with non-linear and non-monotonic delay steps introduce clock skews and decrease overall performance for the IC. Moreover, high resolution delay steps are needed in order to achieve precise timing control. Additionally, it is always desirable to implement a circuit that operates at low power. Existing implementations of delay chain circuits may exhibit some, but not all, of the above desired characteristics and thus suffer from limitations related to timing accuracy or circuit performance. For example, a conventional delay chain circuit can be realized by implementing an inverter chain which is composed of a desired number of invertors. A disadvantage of such a delay chain circuit is that its delay steps are too large and thus cannot be accurately adjusted to meet precise timing requirements.
Therefore, it is desirable to develop delay chain circuits better able to address more of the desired properties, i.e., linear, monotonic, adjustable high resolution delay steps, and low power generation of timing delays.